Integrated circuit designers frequently choose application specific integrated circuit (ASIC) technology when designing integrated circuits to perform unique and customized functions. This is because ASIC technology provides designers with comprehensive tools to customize logic to perform specialized and multiple functions on a single integrated circuit substrate or chip, instead of the multiple chips which typically would be required in the event standardized circuit technology was employed. As will be understood by those skilled in the art, ASICs may be generated in many different ways and have many different designations based on the methods used to design and/or manufacture them. The most time consuming method, but often the one that yields the smallest chip size and/or best performance, is the "full-custom" designed ASIC. These ASICs are often designed entirely from scratch at the transistor level with only occasional use of previously designed circuit "blocks" which are typically referred to as cells, standard cells, or macrocells. Because of this comprehensive approach, custom designed ASICs typically require the creation of an entire design database and test methods (including custom test vectors). A complete set of customized fabrication masks is also typically required for fabrication. These requirements typically make the design and fabrication of custom ASICs very time consuming and expensive when generating prototype devices and when iterating through design changes. Alternative ASIC design methodologies include the use of standard cell technology, which differs from full custom design in that multiple cells or macrocells that have been previously designed are utilized. These cells are selected from libraries of cells for their applicability to the design, and placed and routed with software that is well known in the art. The final circuit then has no fewer custom mask layers than the full custom design method. However, this method does have advantages over the full custom design method in the time required to complete a design, because the elementary level of cell design is only done once to create the libraries, and this work can be reused in multiple subsequent designs.
Alternative application specific integrated circuit design technologies which typically do not incur the time and expense penalties associated with full custom ASICs include gate array technology. Gate array technology typically utilizes the building blocks of logic gates and/or memory devices as resources to minimize design time and cost. This extensive use of blocks enables the gate array designer to focus more on the routing of connections (e.g., metal wiring and interconnects) between these blocks and less on the design and operation of the individual logic gates and other low-level devices. Here, the designer may be able to reduce the number of custom mask layers that must be generated for fabrication because typically only the uppermost masking layers are specific to a particular design. On the other hand, the base masking layers that determine the logic and memory blocks are typically identical for a variety of designs. With these savings comes a penalty since only certain types and sizes of logic gates are typically available to choose from and constraints on the placement of such gates may not always lead to a device having ideal characteristics.
Gate array technology also provides a reduction in the time and expense associated with making design changes through an iterative process. This is because less than all mask layers are involved in any design change at any level, as opposed to the full-custom ASIC design case where design changes may require a change to all mask layers. Notwithstanding these benefits, gate array technology may still require some relatively expensive custom tooling for the upper level masks. Moreover, design checking in physical silicon cannot take place without processing one or more wafers through multiple fabrication steps including deposition, masking and etching, for example, just like full-custom ASIC technology. The terms ASIC and gate array are meant to be interchangeable for the purposes of this disclosure. ASIC or gate array can refer to fully-custom integrated circuits, or semi-custom integrated circuits, including standard cell integrated circuits.
Referring now to FIG. 1, a flow diagram of operations 100 performed when designing a full-custom ASIC will be described. Although the flow diagram displays many decision points and their associated unacceptable paths, the following description does not attempt to elaborate on all the unacceptable paths. As illustrated, a design specification of a desired integrated circuit is initially provided, Block 102, and then from this a HDL/schematic description of the integrated circuit is entered into a design system, Block 104, to generate a complete HDUschematic description, Block 106. From this HDUschematic description, an operation is performed to simulate the functional operation of the integrated circuit, Block 108. The simulation is then checked for accuracy, Block 110. If the simulation is correct, an operation is performed to synthesize logic and generate a logic netlist, Blocks 112 and 114. The synthesis of the logic may require ASIC logic primitives and resources, Block 113, and user synthesis constraints, Block 111. A check may then be performed to determine whether the integrated circuit will receive an internal scan test, Block 116. If so, scan elements can be added to the logic netlist, Block 118. Then, with the addition of ASIC element timing estimates, Block 115, an operation is performed to simulate the timing of the integrated circuit, Block 121. The timing simulation is then checked for accuracy, Block 123. If the simulation is correct, a logic placement and signal routing operation will be performed, Block 120, based on a set of user routing and logic placement constraints, Block 150, and ASIC logic resources and routing resources and constraints, Block 117. From this placement and routing operation, a routed netlist will be generated, Block 122.
A timing extraction operation (e.g., parasitic R and C extraction operation) may then be performed, Block 124, to generate timing parameters, Block 126. The routed netlist and timing parameters are then used to perform another timing simulation, Block 128, which takes into account the actual placement of gates, devices, etc., and interconnect nets which link these devices together. A check is then performed to determine whether the simulation is acceptable, Block 130. If the simulation is acceptable, test vectors are created, Block 140. Operations are also performed to create mask-making data, Block 132. The mask-making data, Block 134, is then used to create masks, Block 136. A prototype of the full-custom ASIC device is then fabricated, Block 138. An operation is then performed to test and evaluate the device and/or system, Block 142. If the test results are acceptable, then the design is complete. However, if the test results are not acceptable, then a check is made to determine whether the HDL/schematic description of the invention (i.e. logic) needs to be modified, the routing and placement needs to be modified, or the synthesis constraints need to be modified, Block 144. If the HDUschematic description needs to be modified, Block 146, then essentially all the above-described steps and operations will need to be repeated. If the synthesis constraints need to be modified, Block 119, then the majority of the above-described steps and operations will need to be repeated from the logic synthesis step, Block 112. But, if only the routing and placement constraints need to be modified, Block 148, then the process can resume at the logic placement and signal routing step, Block 120.
Programmable logic devices (PLDs) may also be used as an alternative application specific integrated circuit design technology. Such devices are also typically referred to as programmable array logic (PAL) and field programmable gate arrays (FPGAs), as described in Chapter 11 of a textbook by Jan M. Rabaey, entitled Digital Integrated Circuits, Prentice Hall, pp. 629-692 (1996), the disclosure of which is hereby incorporated herein by reference. When customizing a PLD, a user typically defines the device within the constraints of the PLD architecture, and then creates through the use of computer aided design tools, a specific set of interconnections or device states at each of the programmable configuration points within the PLD. As will be understood by those skilled in the art, each of these configuration points may be controlled by one or more fuses, antifuses or memory elements, and may be one-time programmable or reprogrammable. The configuration of the PLD is then stored in a configuration file, which is commonly referred to as a "bitstream". This configuration file defines the state of each fuse, antifuse or memory element in the PLD. In the case of PLDs, this bitstream may be programmed into the PLD directly, or in the case of a volatile device, this bitstream may be stored in another device and then read into the PLD upon startup.
An obvious advantage of PLDs is that they require relatively little time and expense to design or generate design iterations. However, for a given functional design, PLDs typically require greater layout area, consume considerably more power and are slower than ASIC technologies (i.e. custom ASIC, standard cell, or gate array). PLDs consume more power and are slower because the signals which traverse programmable elements within the PLD typically encounter higher resistance and capacitance associated with the programmable elements than the resistance and capacitance associated with metal interconnect lines within the gate array and full-custom ASIC technologies. PLDs also require greater layout area because they include additional programmable elements and configuration points.
Referring now to FIG. 2, a flow diagram of operations 200 performed when designing a conventional PLD will be described. As illustrated, a design specification of a desired integrated circuit is initially provided, Block 202, and then from this a HDUschematic description of the integrated circuit is entered into a design system, Block 204, to generate a complete HDL/schematic description, Block 206. From this HDUschematic description, an operation is performed to simulate the functional operation of the integrated circuit, Block 208. The simulation is then checked for accuracy, Block 210. If the simulation is correct, an operation is performed to synthesize logic and generate a logic netlist, Blocks 212 and 214. The synthesis of the logic typically requires PLD logic primitives and resources, Block 213. A logic placement and signal routing operation is then performed, Block 220, based on a set of user routing and logic placement constraints, Block 250, and PLD logic resources and routing resources and constraints, Block 217. From this placement and routing operation, a routed netlist will be generated, Block 222.
A timing extraction operation may then be performed, Block 224, to generate timing parameters, Block 226. The routed netlist and timing parameters are then used to perform a timing simulation, Block 228, which takes into account the actual placement of gates, devices, etc., and interconnect nets which link these devices together. A check is then performed to determine whether the simulation is acceptable, Block 230. If the simulation is acceptable, an operation is performed to generate a bitstream/programming file, Blocks 232 and 234. A prototype of the PLD can then be programmed, Block 236. An operation is then performed to test and evaluate the operation and/or system of the device, Block 242. If the test results are acceptable, then the design of the PLD is complete. However, if the test results are not acceptable, then a check is made to determine whether the HDL schematic description of the circuit needs to be modified or the routing and placement needs to be modified, Block 244. If the HDL schematic description needs to be modified, Block 246, then essentially all the above-described steps and operations of FIG. 2 will need to be repeated. But, if only the routing and placement constraints need to be modified, Block 248, then the process can resume at the logic placement and signal routing step, Block 220.
Unfortunately, as integrated circuit designs such as those having asynchronous inputs increasingly become more complex, the importance of physical testing becomes more important since many of state-of-the-art software simulation tools cannot provide completely accurate simulation. Accordingly, physical designs may need to be redesigned in an iterative manner more frequently, which increases design time and expense. To address these limitations in the ability to accurately and completely simulate highly complex integrated circuits, integrated circuit design methodologies have been developed which include the generation of prototype devices and the performance of small volume production with PLDs. Then, once a final functional design is obtained utilizing the PLD, a conversion is then typically made to full-custom or gate array ASICs for large volume production after the design has been finalized. Unfortunately, a problem with this design methodology is the lack of an efficient technique to provide this conversion from a PLD to a gate array or full-custom ASIC without having to go back to the beginning or HDL/schematic definition stage and repeat the time-consuming and expensive process of generating the gate array or full-custom ASIC to mimic the operation of the PLD. Thus, when switching from a functional PLD implementation to a gate array ASIC implementation, the design process essentially starts over since the logic synthesis operations must be repeated along with the place and route operations and all the other steps in the flow.
This relatively inefficient design methodology is more fully illustrated by FIG. 3. In particular, FIG. 3 illustrates conventional operations 300 which are performed when switching from a PLD implementation to an ASIC implementation. Although the flow diagram displays many decision points and their associated unacceptable paths, the following description does not attempt to elaborate on all the unacceptable paths. These operations include the step of selecting a PLD for conversion, Block 302, with the description of the PLD being defined by a HDUschematic description, Block 304. A check is then made to determine whether the HDUschematic format of the PLD is compatible with the format for specifying an ASIC, Block 306. If the formats are not compatible, then the HDUschematic of the PLD undergoes a conversion process, Block 308, to generate a converted format for the desired ASIC, Block 349. From this HDL/schematic description, an operation is performed to simulate the functional operation of the integrated circuit, Block 350. The simulation is then checked for accuracy, Block 352. If the simulation is correct, an operation is performed to synthesize logic and generate a logic netlist, Blocks 312 and 314. The synthesis of the logic may require ASIC logic primitives and resources, Block 313, and the user synthesis constraints, Block 311. A check may then be performed to determine whether the integrated circuit will receive an internal scan test, Block 316. If so, scan elements will be added to the logic netlist, Block 320. Then, with the addition of the ASIC element timing estimates, Block 315, an operation is performed to simulate the timing of the integrated circuit, Block 317. The timing simulation is then checked for accuracy, Block 323. If the timing simulation is not correct, a check is made at Block 343 to determine whether the synthesis constraints need to be modified, Block 325, or whether the logic needs to be modified. However, if the simulation is correct, a logic placement and signal routing operation will be performed, Block 318, based on a set of user routing and logic placement constraints, Block 321, and ASIC logic resources and routing resources and constraints, Block 319. From this placement and routing operation, a routed netlist will be generated, Block 322.
A timing extraction operation (e.g., parasitic R and C extraction operation) may then be performed, Block 324, to generate timing parameters, Block 326. The routed netlist and timing parameters are then used to perform another timing simulation, Block 328, which takes into account the actual placement of gates, devices, etc., and interconnect nets which link these devices together. A check is then performed to determine whether the simulation is acceptable, Block 330. If the simulation is acceptable, test vectors are created, Block 342. Operations are also performed to create mask-making data, Block 332. The mask-making data, Block 334, is then used to create masks, Block 336. A prototype of the ASIC device is then fabricated, Block 338. An operation is then performed to test and evaluate the operation of the device and/or the device within the application, Block 340. If the test results are acceptable, then the design is complete. However, if the test results are not acceptable, then a check is made to determine whether the HDL/schematic description of the invention (i.e. logic) needs to be modified, the routing and placement needs to be modified, or the synthesis constraints need to be modified, Block 344. If the HDL schematic description needs to be modified, Block 346, then essentially all the above-described steps and operations will need to be repeated. If the synthesis constraints need to be modified, Block 325, then the majority of the above-described steps and operations will need to be repeated from the logic synthesis step, Block 312. But, if only the routing and placement constraints need to be modified, Block 348, then the process can resume at the logic placement and signal routing step, Block 318.
Alternative methods of converting PLDs to ASICs have been devised that reduce the workload in the conversion process by creating parameterized software models for elements of the PLD such as described in U.S. Pat. No. 5,815,405 to Baxter titled "Method and apparatus for converting a programmable logic device representation of a circuit into a second representation of the circuit". These methods attempt to allow the reuse of work product in the same way that standard cell ASIC technology allows the reuse of work product. Standard cell ASIC technology reuses previously created cells or macrocells and allows the designer to reuse these higher level previously designed building blocks, lessening the design effort over full custom design. In the same way, Baxter proposes reusing previously designed software macros of the logic elements within the PLD, and creating a software model of the design from the bitstream of the PLD, relieving the designer of these repetitive tasks. These methods however still suffer from the limitations that they require the user to complete the multiple steps of synthesis and place and route after the software model has been created, and do not guarantee that equivalent logic implementation and timing, or relative placement and relative routing delays of signals will be maintained between the target PLD representation being converted and the ASIC device as converted.
In particular, U.S. Pat. No. 5,815,405 to Baxter discloses an apparatus which parses a device specific bitwise representation used to program a PLD. The apparatus identifies various configurable elements being programmed by the bitwise representation, and identifies the actual configuration of the identified elements. As illustrated by FIG. 1B of the '405 patent, for each configurable element represented in the bitwise representation, a new instance of that type of element is included in a pre-compiled representation 137 of the circuit design. This pre-compiled representation, which is independent of the target fabrication technology, may be an HDL representation or a netlist representation. A compiler then uses a target fabrication technology library 142 to convert the pre-compiled representation 137 into a post-compiled representation 147. A place and route tool 150 is then used to place and route the post-compiled representation 147 in the desired target technology. Unfortunately, like the relatively inefficient design methodology of FIG. 3, expensive and time consuming operations are still required to convert from an HDL or netlist representation of the desired circuit to a design which is compatible with the target technology. Conventional place and route operations are also required.
Thus, notwithstanding the above-described techniques for designing integrated circuits, there still continues to be a need for design techniques which enable more efficient conversion of PLD-based designs to functionally equivalent ASIC designs.